Storage device having a controller configured to select modes as write modes based on received instructions, storage system, and control method

ABSTRACT

According to one embodiment, a storage device includes a nonvolatile memory and a controller. The controller is configured to select a first mode as a write mode to write data from the host to the nonvolatile memory when the controller receives a first instruction from the host. In the first mode, n-bit data is written into a memory cell in a first area of the nonvolatile memory, n being a positive integer more than or equal to 1. The controller is configured to select another mode different from the first mode as the write mode when the controller receives a second instruction from the host.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No.17/201,559, filed Mar. 15, 2021, which is based upon and claims thebenefit of priority from Japanese Patent Application No. 2020-109978,filed Jun. 25, 2020, the entire contents of which are incorporatedherein by reference.

FIELD

Embodiments described herein relate generally to a technology to controla nonvolatile memory.

BACKGROUND

A solid-state drive (SSD) including a nonvolatile memory is known as oneof storage devices. The SSD receives data from a host device(hereinafter referred to as a host) and writes it to the nonvolatilememory.

An SSD including first and second write modes has been developed. In thefirst write mode, priority is given to a write speed. In the secondwrite mode, priority is given to a data write size. The SSD selects oneof the write modes based on a write state and the like.

However, the SSD determines its selection timing of the write mode.Therefore, write performance may not be increased at a timing desired bythe host.

Embodiments described herein aim to provide a storage device, a storagesystem and a control method, which are capable of increasing writeperformance at a timing desired by a host.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing an exemplary configuration of astorage system including a storage device according to a firstembodiment.

FIG. 2 is a block diagram showing an exemplary configuration of a NANDflash memory included in the storage device according to the firstembodiment.

FIG. 3 is a block diagram showing another exemplary configuration of theNAND flash memory included in the storage device according to the firstembodiment.

FIG. 4A is a block diagram showing an exemplary configuration of an SLCbutter included in the NAND flash memory included in the storage deviceaccording to the first embodiment.

FIG. 4B is a block diagram showing another exemplary configuration ofthe SLC buffer included in the NAND flash memory included in the storagedevice according co the first embodiment.

FIG. 5 is a flowchart showing an example of a write operation of a hostof the storage system according to the first embodiment.

FIG. 6 is a flowchart showing an example of a write operation of thestorage device of the storage system according to the first embodiment.

FIG. 7A is a graph showing an example of changes in the number of freeblocks and a write performance in a comparative example where an SSDsets a write mode.

FIG. 7B is a graph showing an example of changes in the number of thefree blocks and the write performance in the first embodiment.

FIG. 6 is a flowchart showing another example of the write operation ofthe host of the storage system according to the first embodiment.

FIG. 9 is a flowchart showing an example of a write operation of a hostof a storage system according to a second embodiment.

FIG. 10 is a flowchart showing an example of a write operation of thestorage device of the storage system according to the second embodiment.

FIG. 11A is a graph showing an example of changes in the number of freeblocks and a write performance in a comparative example where an SSDsets a write mode.

FIG. 11B is a graph showing an example of changes in the number of thefree blocks and the write performance in the second embodiment.

FIG. 12 is a flowchart showing an example of a write operation of a hostof a storage system according to a third embodiment.

FIG. 13 is a flowchart showing an example of a write operation of thestorage device of the storage system according to the third embodiment.

FIG. 14 is a flowchart showing an example of a write operation of astorage device of a storage system according to a fourth embodiment.

FIG. 15A is the graph showing the example of changes in the number offree blocks and the write performance in the first embodiment.

FIG. 15B is a graph showing an example of changes in the number of thefree blocks and the write performance in the fourth embodiment.

FIG. 16 is a flowchart showing another example of the write operation ofthe host of the storage system according to the fourth embodiment.

FIG. 17 is a flowchart showing another example of the write operation ofthe storage device of the storage system according to the fourthembodiment.

FIG. 18 is a flowchart showing an example of a write operation of a hostof a storage system according to a fifth embodiment.

FIG. 19 is a flowchart showing an example of a write operation of astorage device of the storage system according to the fifth embodiment.

FIG. 20A is a graph showing an example of changes in the number of freeblocks and a write performance in the fourth embodiment shown in FIG.15B.

FIG. 20B is a graph showing an example of changes in the number of thefree blocks and the write performance in the fifth embodiment.

FIG. 21 is a flowchart showing an example of a write operation of a hostof a storage system according to a sixth embodiment.

FIG. 22 is a flowchart showing an example of a write operation of astorage device of the storage system according to the sixth embodiment.

FIG. 23A is a graph showing an example of changes in the number of freeblocks and a write performance in the fourth embodiment shown in FIG.15B.

FIG. 23B is a graph showing an example of changes in the number of thefree blocks and the write performance in the sixth embodiment.

FIG. 24 is a flowchart showing an example of a write operation of a hostof a storage system according to a seventh embodiment.

FIG. 25 is a flowchart showing an example of a write operation of astorage device of the storage system according to the seventhembodiment.

FIG. 26A is a graph showing an example of changes in the number of freeblocks and a write performance in the sixth embodiment shown in FIG.23B.

FIG. 26B is a graph showing an example of changes in the number of thefree blocks and the write performance in the seventh embodiment.

FIG. 27 is a flowchart showing an example of a write operation of a hostof a storage system according to an eighth embodiment.

FIG. 28 is a flowchart showing an example of a write operation of astorage device of the storage system according to the eighth embodiment.

FIG. 29A is a graph showing an example of changes in the number of freeblocks and a write performance in the fourth embodiment shown in FIG.15B.

FIG. 29B is a graph showing an example of changes in the number of thefree blocks and the write performance in the eighth embodiment.

FIG. 30 is a flowchart showing an example of a write operation of a hostof a storage system according to a ninth embodiment.

FIG. 31 is a flowchart showing an example of a write operation of astorage device of the storage system according to the ninth embodiment.

FIG. 32 illustrates the example of the write operation of the storagedevice according to the ninth embodiment.

FIG. 33 is a flowchart showing an example of a write operation of a hostof a storage system according to a tenth embodiment.

FIG. 34 is a flowchart showing an example of a write operation of astorage device of the storage system according to the tenth embodiment.

FIG. 35 illustrates the example of the write operation of the storagedevice according to the tenth embodiment.

DETAILED DESCRIPTION

Embodiments will be described below with reference to the drawings. Inthe following description, a device and a method are illustrated toembody the technical concept of the embodiments, and the technicalconcept is not limited to the configuration, shape, arrangement,material, etc., of the structural elements described below.Modifications that could easily be conceived by a person with ordinaryskill in the art are naturally included in the scope of the disclosure.

To make the description clearer, the drawings may schematically show thesize, thickness, planer dimension, shape, etc., of each elementdifferently from those in the actual aspect. The drawings may includeelements that differ in dimension and ratio. Elements corresponding toeach other in the drawings are denoted by the same reference numeral andthe overlapping descriptions may be omitted. Some elements may bedenoted by different names, and these names are merely an example. Itshould not be denied that one element is denoted by different names.Note that “connected” in the following description means that oneelement is connected to another element via still another element aswell as that one element is directly connected to another element.

In general, according to one embodiment, a storage device includes anonvolatile memory and a controller. The controller is configured toselect a first mode as a write mode to write data from the host to thenonvolatile memory when the controller receives a first instruction fromthe host. In the first mode, n-bit data is written into a memory cell ina first area of the nonvolatile memory, n being a positive integer morethan or equal to 1. The controller is configured to select another modedifferent from the first mode as the write mode when the controllerreceives a second instruction from the host.

FIRST EMBODIMENT

The configuration of a storage system 1 including a storage deviceaccording to a first embodiment will be described. FIG. 1 is a blockdiagram showing an exemplary configuration of the storage system 1including a storage device according to the first embodiment. Thestorage device is a semiconductor storage device configured to writedata to a nonvolatile memory and read data from the nonvolatile memory.The nonvolatile memory is not limited to such an example but includes aNAND type flash memory. Hereinafter, the nonvolatile memory will bereferred to as a NAND flash memory. The semiconductor storage device inthis embodiment is an SSD 3 including a NAND flash memory 5.

The storage system 1 includes a host 2 and the SSD 3. The host 2 is aninformation processing device configured to control the SSD 3. The host2 is, for example, a personal computer, a server computer, a mobileterminal, and an in-vehicle device.

An example in which the SSD 3 is connected to the host 2 via a cable isshown in FIG. 1 . The SSD 3 may be connected to the host 2 via a networkor may be built in the host 2.

An interface for connecting the host 2 and the SSD 3 is not limited toone in this embodiment. SATA (serial ATA), an SAS (serial attachedSCSI), a UFS (universal flash storage), PCI Express (PCIe) (™), andEthernet (™) can be used.

The SSD 3 includes a controller 4, the NAND flash memory 5, and a DRAM6.

The NAND flash memory 5 includes a plurality of memory cells arranged ina matrix. The NAND flash memory 5 may be a flash memory having atwo-dimensional structure or a flash memory having a three-dimensionalstructure. The NAND flash memory 5 may include a plurality of NAND flashmemory chips, i.e. a plurality of NAND flash memory dies. Each of thechips may be implemented as a flash memory configured to store data ofone or more bits per memory cell.

The flash memory configured to store data of one bit per memory cell isreferred to as a single-level cell (SLC) flash memory capable of storingdata of one bit per memory cell. The flash memory configured to storedata of a plurality of bits per memory cell includes a multi-level cell(MLC or 4LC) flash memory, a triple-level cell (TLC or 8LC) flashmemory, a quad-level cell (QLC or 16LC) flash memory, a flash memory, aflash memory capable of storing data of five bits or more per memorycell, and the like. The MLC (or 4LC) flash memory is capable of storingdata of two bits per memory cell. The TLC (or 8LC) flash memory iscapable of storing data of three bits per memory cell. The QLC (or 16LC)flash memory is capable of storing data of four bits per memory cell.Although a flash memory that stores data of two or more bits per memorycell is sometimes referred to as an MLC flash memory, a flash memorythat stores data of two bits per memory cell will be referred to as anMLC flash memory hereinafter.

The memory cell array of the NAND flash memory 5 includes a plurality ofblocks BLK0 to BLKx-1. Each of the blocks BLK0 to BLKx-1 includes aplurality of pages P0 to Py-1. Each of the pages P0 to Py-1 includes aplurality of memory cells connected to the same word line. Each of theblocks BLK0 to BLKx-1 is a minimum unit of data erase operation forerasing data from the NAND flash memory 5. The blocks may be referred toas “erase blocks”, “physical blocks” or “physical erase blocks”. Each ofthe pages is a minimum unit of data write operation and data readoperation. Note that the word line may be defined as a unit of datawrite operation and data read operation.

There is a limit to the maximum number of program/erase cycles allowedfor each of blocks BLK0 to BLKx-1. One program/erase cycle of a blockincludes an erase operation for bringing all memory cells in the blockinto an erased state and a write operation, more specifically, a programoperation, for writing data to each page of the block.

The controller 4 may be implemented by a circuit such as asystem-on-a-chip (SoC). The controller 4 is electrically connected tothe NAND flash memory 5 via a NAND interface (I/F) circuit 13. The NANDI/F circuit 13 is not limited to one in this embodiment, but based on atoggle NAND flash interface and an open NAND flash interface (GNFI). TheNAND I/F circuit 13 is connected to each of a plurality of NAND flashmemory chips in the NAND flash memory 5 via a plurality of channels(Ch). Since the NAND flash memory chips are driven in parallel, accessto the NAND flash memory 5 can be broadened. The NAND I/F circuit 13includes an ECC processor 13. Though an example in which the ECCprocessor 18 is provided in the NAND I/F circuit 13 will be described,it may be provided in the controller 4.

The ECC processor 18 can be implemented as a circuit having a functionof protecting data written into the NAND flash memory 5 and data readfrom the NAND flash memory 5 using an error correction code (ECC). TheECC processor 18 adds an ECC to data written into the NAND flash memory5. The ECC processor 18 also determines whether an error is included indata read from the NAND flash memory 5, using an ECC added to the readdata. If an error is included, the ECC processor 18 corrects the error.

The controller 4 controls the NAND flash memory 5.

The controller 4 includes a host interface (I/F) circuit 11, a CPU 12, aDRAM interface (I/F) circuit 14, a direct memory access controller(DMAC) 15, and a static RAM (SRAM) 16 as well as the NAND I/F circuit13. The host I/F circuit 11, CPU 12, NAND I/F circuit 13, DRAM I/Fcircuit 14, DMAC 15, and SRAM 16 are connected to each other via a bus10.

The host I/F circuit 11 is configured to execute communications with thehost 2. The host I/F circuit 11 is, for example, an SATA interfacecontroller, an SAS interface controller, a PCIe controller, and anEthernet controller.

The host I/F circuit 11 receives various commands from the host 2. ATAcommands defined by the ATA standard are used in the SATA interface,SCSI commands defined by the SCSI standard are used in the SASinterface, and NVMe commands defined by the NVM Express (NVMe)™ standardare used in the PCIe and Ethernet interfaces.

The CPU 12 is configured to control the host interface 11, NAND I/Fcircuit 13, and DRAM interface 14. The CPU 12 executes a control program(firmware) stored in, e.g. a ROM (not shown) to execute variousoperations. The CPU 12 can function as a write controller 22 and agarbage collection (hereinafter referred to as GC)/compaction controller26.

The SSD 3 includes a dynamic random access memory (DRAM 6) as a randomaccess memory (RAM) that is a volatile memory. A random access memorysuch as a static random access memory (SRAM) may be built in thecontroller 4. Note that the DRAM 6 may be built in the controller 4.

The DRAM 6 includes a write buffer 32 for temporarily storing data to bewritten into the NAND flash memory 5.

The DRAM 6 also includes a cache area of a lookup table (L2P Table) 34which functions as a logical-to-physical address conversion table. Thelogical address is an address used by the host 2 to specify a logicaladdress in the logical address space of the SSD 3. As the logicaladdress, a logical block address (LBA: Logical Block Address) can beused. The L2P table 34 manages mapping between each logical address(hereinafter referred to as LBA) and each physical address (PBA:Physical Block Address) of the NAND flash memory 5.

The controller 4 may function as a flash translation layer (FTL)configured to execute data management and block management of the NANDflash memory 5.

The data management executed by the FTL includes (1) management ofmapping information indicating a correspondence between each LBA andeach PBA of the NAND flash memory 5 and (2) an operation for hidingconstraints of the NAND flash memory 5. The constraints include, forexample, a read/write operation for each page and an erase operation foreach block.

The controller 4 uses the L2P table 34 to manage mapping between eachLBA and each PBA. The PBA corresponding to an LBA represents the latestphysical storage location in the NAND flash memory 5 into which datacorresponding to the LBA is written. The L2P table 34 may be loaded fromthe NAND flash memory 5 into the DRAM 6 when the SSD 3 is powered on.

In the NAND flash memory 5, data can be written into a page only onceper erase cycle (program/erase cycle) of a block including the page.That is, new data cannot be overwritten directly on the area in a blockinto which data has already been written. In order to update dataalready written into a block, therefore, the controller 4 writes newdata into an unwritten area in the block (or another block) and managesthe previous data as invalid data. In other words, the controller 4writes update data corresponding to an LBA into another physical storagelocation, not into a physical storage location in which the previousdata corresponding to the LBA is stored. Then, the controller 4 updatesthe L2P table 34 to associate the LBA with a PBA indicating anotherphysical storage location and invalidates the previous data.

The invalid data means data stored in a physical storage location whichis not referred to from the L2P table 34. For example, data stored in aphysical storage location which is not referred to from the L2P table34, i.e. data that is not associated with the LBA as current data, isinvalid data. The invalid data may no longer be read from the host 2.When update data is stored in a logical area associated with an LBA, thevalid data stored so far in the logical, area is invalidated, and theupdate data is validated.

The valid data means the latest data corresponding to an LBA. Forexample, data stored in a physical storage location that is referred tofrom the L2P table 34, that is, data associated with an LBA as currentdata, is valid data. The valid data may be read from the host 2 later.

The block management executed by the FTL includes defective blockmanagement, a wear leveling, and a GC operation.

The wear leveling makes the number of times of rewrite (the number ofprogram/erase cycles) of each block uniform.

The GC operation decreases the number of blocks in which valid data andinvalid data are mixed and increases the number of the free blocks. Thefree blocks do not contain valid data. The free blocks can be used aswrite destination blocks of new data after a data erase operation isexecuted. On the other hand, a block that stores valid data is an activeblock.

The NAND flash memory 5 can execute a write operation in a plurality ofwrite modes that vary depending on how many bits of data are written permemory cell. The write modes include, for example, an SLC mode, an MLCmode, a TLC mode, a QLC mode, and a write mode in which data of fivebits or more is written per memory cell. In the SLC mode, data of onebit is written per memory cell. In the MLC mode, data of two bits iswritten per memory cell. In the TLC mode, data of three bits is writtenper memory cell.

In the QLC mode, data of four bits is written per memory cell.

For example, the NAND flash memory 5 may be implemented as an MLC flashmemory (i.e. a 4LC flash memory) capable of storing data of two bits permemory In this case, usually, lower page data and upper page data, whichare data for two pages, are written into a plurality of memory cellsconnected to the same word line. Thus, data of two bits can be writtenper memory cell. A freely selected area, e.g. one or more freelyselected blocks, in the MLC flash memory can be used as an SLC areacapable of storing data of only one bit per memory cell.

In the write operation of writing data into the SLC area, data for onlyone page is written into a plurality of memory cells connected to thesame word line. Thus, in each block used as the SLC area, as in eachblock (i.e. SLC block) in the SLC flash memory, data of only one bit canbe written per memory cell. As a result, each block used as the SLC areafunctions as an SLC block.

Alternatively, the NAND flash memory 5 may be a TLC flash memory (8LCflash memory) capable of storing data of three bits per memory cell.

In this case, usually, lower page data, middle page data, and upper pagedata, which are data for three pages, are written into a plurality ofmemory cells connected to the same word line. Thus, data of three bitscan be written per memory cell. A freely selected area, e.g. one or morefreely selected blocks, in the TLC flash memory can be used as theforegoing SLC area or an MLC area capable of storing data of two bitsper memory cell. The SLC and MLC areas may be set in units smaller thanblocks. For example, the SLC and MLC areas may be set in units of wordlines or units of sets of word lines in a block. In the MLC area, dataof only two pages is written into a plurality of memory cells connectedto the same word line. Data of only two bits can thus be written intothe MLC area per memory cell.

Alternatively, the NAND flash memory 5 may be a QLC flash memory (16LCflash memory) capable of storing data of four bits per memory cell.

In this case, usually, data for four pages is written into a pluralityof memory cells connected to the same word line. Thus, data of four bitscan be written per memory cell. A freely selected area (e.g. one or morefreely selected blocks) in the QLC flash memory can be used as theforegoing SLC or MLC area, or a TLC area capable of storing data ofthree bits per memory cell. The SLC, MLC, and TLC areas may De set inunits smaller than blocks. For example, the SLC, MLC, and TLC areas maybe set in units of word lines or units of sets of word lines in a block.In the TLC area, data of only three pages is written into a plurality ofmemory cells connected to the same word line. Data of three bits canthus be written into the TLC area per memory cell.

The storage density per memory cell in each write mode is 2 values (i.e.one page per word line) in the SLC mode, 4 values (i.e. two pages perword line) in the MLC mode, 8 values (i.e. three pages per word line) inthe TLC mode, and 16 values (i.e. four pages per word line) in the QLCmode. The higher the storage density, the lower the data write speed andread speed for the NAND flash memory 5. The lower the storage density,the higher the data write speed and read speed. In these four modes,therefore, the data write and read speed is the lowest in the QLC mode,and it is the highest in the SLC mode.

The higher the storage density, the shorter the life (or endurance) ofthe NAND flash memory 5. The lower the storage density, the longer thelife. The lower the storage density, the wider a margin betweenthreshold voltage distributions corresponding to adjacent states. Thehigher the storage density, the narrower the margin. The wide marginsuppresses an increase in the probability that data of a memory cellwill be read out as erroneous data even though the threshold voltage ofthe memory cell is shifted by stress to be applied to the memory cell.

Thus, for example, the degree of wear-out of each memory cell, which isallowable in the SLC mode, is higher than that of each memory cell whichis allowable in the QLC mode. Therefore, when a low storage densitywrite mode having a wide margin between threshold voltage distributionsis used, the endurance of the NAND flash memory 5 can be made longerthan when a high storage density write mode having a narrow marginbetween threshold voltage distributions is used. That is, the allowablemaximum number of program/erase cycles can be increased when the lowstorage density write mode is used.

The endurance of the NAND flash memory 5 is the shortest in the QLC modeof the four modes, and the endurance is the longest in the SLC modethereof. For example, the maximum number of program/erase cycles allowedwhen data is written in the QLC mode is several thousands cycles, andthe maximum number of program/erase cycles allowed when data is writtenin the SLC mode is several tens of thousands cycles.

Note that the NAND flash memory 5 may be configured to store data offive bits or more per memory cell. In this case, too, a freely selectedarea in the NAND flash memory 5 can be used as an area into which dataof only four bits or less is written per memory cell.

An example of the storage capacity of the NAND flash memory 5corresponding to each of the write modes will be described. Here, it isassumed that the NAND flash memory chips included in the NAND flashmemory 5 are implemented as a QLC flash memory configured to store dataof four bits per memory cell. It is also assumed that when data iswritten into the NAND flash memory 5 in the QLC mode, the storagecapacity of the SSD 3 is 512 GB.

Under optimum conditions without defective blocks or the like, thestorage capacity of the SSD3 is 384 GB when data is written into theNAND flash memory 5 in the TLC mode, it is 256 GB when data is writtenin the MLC mode, and it is 128 GB when data is written in the SLC mode.

As described above, the storage capacity of the NAND flash memory 5varies depending on which write mode is used to write data.

In the first embodiment, as a write mode of the NAND flash memory 5, oneof first and second write modes which differ in the number of datastorable bits per memory cell can be selected. The first write mode is aperformance-priority write mode for improving the write performance (andread performance) of the SSD3 in which the number of data storable bitsper memory cell is small. The second write mode is a capacity-prioritywrite mode for increasing the storage capacity in which the number ofdata storable bits per memory cell is large. The followings are examplesof combinations of the first and second write modes when the NAND flashmemory 5 has the SLC, MLC, TLC, and QLC modes as write modes.

In the first combination, the first write mode is the SLC mode and thesecond write mode is the MLC mode.

In the second combination, the first write mode is the SLC mode and thesecond write mode is the TLC mode.

In the third combination, the first write mode is the SLC mode and thesecond write mode is the QLC mode.

In the fourth combination, the first write mode is the MLC mode and thesecond write mode the TLC mode.

In the fifth combination, the first write mode is the MLC mode and thesecond write mode is the QLC mode.

In the sixth combination, the first write mode is the TLC mode and thesecond write mode is the QLC mode.

In the following description, the first write mode (orperformance-priority write mode) is the SLC mode and the second writemode (or capacity-priority write mode) is the TLC mode. Conventionally,an SSD determined which of the first and second write modes should beused. For example, when the SSD continues random access or receives alarge amount of write data, it may select the performance-priority writemode to maintain the write speed. For example, the amount of use of freeblocks by executing a write operation in the performance-priority writemode is larger than that in the capacity-priority write mode.

In a conventional storage system, the SSD 3 has selected the write modeof the NAND flash memory 5 based on a certain strategy. However, thereis no guarantee that the selection result of the SSD 3 matches thedesire of the host 2. Before the host 2 desires writing in theperformance-priority write mode, the SSD 3 may execute a write operationin the performance-priority write mode and use free blocks of the NANDflash memory 5. In this case, the number of writable blocks is limitedand thus the SSD 3 cannot select the performance-priority write modewhen the host 2 desires writing in the performance-priority write mode,but it has to select the capacity-priority write mode.

In the first embodiment, the host 2 is configured to designate a writemode of the NAND flash memory 5, as will be described later.

The outline of the write operation of the NAND flash memory 5 will bedescribed. As an example of the write mode, a case where the SLC mode isused as the performance-priority write mode and the TLC mode is used asthe capacity-priority write mode, will be described. Each block of theNAND flash memory 5 can be used as both a TLC block and the SLC block.

Write data sent to the SSD 3 from the host 2 is stored temporarily inthe write buffer 32. The write data read from the write buffer 32 iswritten into a write destination block of the NAND flash memory 5.

FIG. 2 shows an example of a write operation when the write mode of theNAND flash memory 5 is set to the SLC mode. When the write mode has beenset to the SLC mode, write data is written into an SLC write destinationblock 102. The SLC write destination block 102 is the SLC block.

FIG. 3 shows an example of a write operation when the write mode of theNAND flash memory 5 is set to the TLC mode. When the write mode is setto the TLC mode, write data is written into a TLC write destinationblock 126. The TLC write destination block 126 is the TLC block.

As shown in FIGS. 2 and 3 , the NAND flash memory 5 includes an activeblock pool 104 and a free block pool 116. The controller 4 allocateseach block BLK of the NAND flash memory 5 to the active block pool 104or the free block pool 116. The active block pool 104 includes one ormore SLC blocks 106 and one or more TLC blocks 108. The free block pool116 includes one or more free blocks 118.

The controller 4 executes a data erase operation for one of the freeblocks 118 allocated to the free block pool 116, and then allocates theerased block to the SLC write destination block 102 or the TLC writedestination block 126.

The controller 4 allocates the SLC write destination block 102 or theTLC write destination block 126 to the active block pool 104 when thereis no space for writing new data in the SLC write destination block 102or the TLC write destination block 126, that is, when the SLC writedestination block 102 or the TLC write destination block 126 is filledwith write data.

In order to increase the number of the free blocks allocated to the freeblock pool 116, a GC or a compaction is executed. In the GC/compaction,the controller 4 sets one of the SLC blocks 106 or one of the TLC blocks108, which are allocated to the active block pool 104, as a copy sourceblock 112. For example, the controller 4 may use a block having lessvalid data as a copy source block among active blocks in which validdata and invalid data are mixed. The controller 4 sets one of the freeblocks 118 allocated to the free block pool 116 as a copy destinationblock 114.

The controller 4 copies the valid data of the copy source block 112 tothe copy destination block 114. The controller 4 updates the L2P table34 to map a PBA of the copy destination block 114 to each LBA of thevalid data of the copied copy source block 112. When the valid data iscopied to the copy destination block 114, the copy source block 112includes only invalid data and is allocated to the free blocks.

Since each block can be used as both the TLC block or the SLC block, ablock allocated to the SLC write destination block 102 need not be fixedto a specific one. The copy source block of the GC/compaction forgenerating a free block to be allocated to the SLC write destinationblock 102 is not limited to the SLC block, but may be the TLC block.Since the SLC block stores only 33% of the data stored in the TLC block,the amount of data to be copied is small, with the result that there isa strong possibility that the SLC block will be selected as a copysource block. If, however, the ratio of invalid data in the TLC block ishigh and that of valid data therein is low, the TLC block may beselected as a copy source block. For example, a block BLK0 may beallocated to the SLC write destination block 102, and set to the SLCactive block 106 and then changed to the free block 118 by theGC/compaction, and then allocated to the TLC write destination block126. This is referred to as an SLC/TLC selecting system. In the SLC/TLCselecting system, the free block pool 116 can be used as the SLC blockand the TLC block.

In contrast to the above, there is a system in which a block to beallocated to the SLC write destination block 102 is determined to be aspecific block, such as blocks BLK0 to BLK99. This system will bereferred to as an SLC fixing system. In the SLC fixing system, a freeblock pool for the SLC write destination block and a free block pool forthe TLC write destination block need to be separated from each other.The GC/compaction for making a free block for the SLC write destinationblock 102 and the GC/compaction for making a free block for the TLCwrite destination block 126 are different operations.

The first embodiment is applicable to both the SLC/TLC selecting systemand the SLC fixing system.

The operation of selecting the SLC block as the copy source block 112and rewriting data of the SLC buffer into the TLC block by the GCoperation may be referred to as a compaction operation. In thisspecification, however, an operation of copying valid data of the copysource block 112 that is an active block to the copy destination blockand generating a free block by setting the copy source block as the freeblock, is generally referred to as the GC/compaction.

In the NAND flash memory 5, a set of blocks used as the SLC block willbe referred to as the SLC buffer. The SLC buffer includes a block whichis originally the TLC block and into which data is temporarily writtenin the SLC mode. The data written into the SLC block in the SLC bufferis rewritten to the TLC block in the TLC mode by the GC/compaction.

FIGS. 4A and 48 are block diagrams illustrating the concept of the SLCbuffer. FIG. 4A shows an example of the SLC buffer 122 when the writemode of the NAND flash memory 5 is set to the SLC mode. In this example,the SLC buffer 122 includes the SLC write destination block 102, whichis a write destination block of write data, and the SLC block 106 intowhich write data has already been written. The blocks other than the SLCbuffer 122 of the NAND flash memory 5 include TLC blocks 108.

FIG. 4B shows an example of the SLC buffer 122 when the write mode ofthe NAND flash memory 5 is set to the TLC mode. In this example, the SLCbuffer 122 includes the SLC blocks 106 to which write data has alreadybeen written. The blocks other than the SLC buffer 122 of the NAND flashmemory 5 includes the TLC block 108 and a TLC write destination block126.

As described above, since the storage capacity of the SLC blocks 102 and106 is 1/3 of the storage capacity of the TLC blocks 126 and 108, thestorage capacity of the SSD 3 decreases as the number of blocks of theSLC buffer 122 increases. In order to prevent the storage capacity ofthe SSD 3 from being equal to or smaller than a predetermined capacity,an upper limit can be set for the number of blocks of the SLC buffer122.

FIG. 5 is a flowchart showing an example of the write operation of thehost 2 in the storage system 1 according to the first embodiment. FIG. 6is a flowchart showing an example of the write operation of the SSD 3 inthe storage system 1 according to the first embodiment.

As shown in FIG. 5 , the host 2 sets a target period during which thehost 2 desires high write performance, an SLC write disable time, and anSLC write enable time in S102. An operating system (OS) of the host 2that drives an SSD driver (NVMe driver, SATA drivers, etc.) or anapplication program of the host 2 can determine the target period. Theuser or operator of the host 2 may decide the target period and input itto the host 2. Then, the host 2 sets the start of the target period or atime immediately before the target period as the SLC write enable time.The host 2 sets any time before the SLC write enable time as the SLCwrite disable time.

In S104, the host 2 determines whether a current time is the SLC writedisable time. If the host 2 determines that the current time is not theSLC write disable time (NO in S104), the host 2 repeats thedetermination in S104 until the SLC write disable time.

If the host 2 determines that the current time is the SLC write disabletime (YES in S104), the host 2 sends the SLC write disable command tothe SSD 3 in S106. The host 2 may send the write command to the SSD 3after S106 if there is data to be written.

After S106, the host 2 determines in S108 whether a current time is theSLC write enable time. If the host 2 determines that the current time isnot the SLC write enable time (NO in S108), the host 2 repeats thedetermination in S108 until the SLC write enable time.

If the host 2 determines that the current time is the SLC write enabletime (YES in S108), the host 2 sends an SLC write enable command to theSSD 3 in S110. The host 2 sends the write command to the SSD 3 in S112and ends the operation. Note that the operation in S112 is executed whenthere is data to be written. Thus, the host 2 may execute the operationin S112 a plurality of times or may not execute the operation in S112 atall.

In the SSD 3, as shown in FIG. 6 , upon receiving the SLC write disablecommand from the host 2 in S122, the controller 4 sets the write mode tothe TLC mode in S124. After that, upon receiving the write data from thehost 2, the controller 4 writes the data into the TLC write destinationblock 126 of the NAND flash memory 5, as shown in FIG. 3 .

Upon receiving the SLC write enable command from the host 2 in S126, thecontroller 4 determines in S128 whether the free block pool 116 includesa sufficient number of the free blocks 118. Specifically, the controller4 determines whether the number of the free flocks exceeds apredetermined number. This number relates to the conditions under whicha write operation can be executed in the SLC mode, and may be ten, forexample. If the number of the free blocks 118 in the free block pool 116is larger than ten, a write operation can be executed in the SLC mode.If the number is ten or smaller, the write operation cannot be executedin the SLC mode.

If the controller 4 determines that the free block pool 116 does notinclude a sufficient number of the free blocks (NO in S128), thecontroller 4 returns an error signal to the host 2 in S130. After S130,the controller 4 ends the operation.

If the controller 4 determines that the free block pool 116 includes asufficient number of the free blocks (YES in S128), the controller 4sets the write mode of the write data to the SLC mode in S132. Thecontroller 4 returns information indicating that the write mode has beenset to the SLC mode to the host 2 in S134.

Upon receiving the write command from the host 2 in S135, the controller4 writes the data into the SLC write destination block 102 of the NANDflash memory 5 in S136, as shown in FIG. 2 . After S-136, the controller4 ends the operation. If the controller 4 receives no write command fromthe host 2, the controller 4 does not execute the operations in S135 andS136.

Although not shown in the flowchart, when the number of the free blocksbecomes equal to or smaller than a predetermined number, the controller4 may change the write mode of the write data to the TLC mode regardlessof a mode control instruction from the host 2. When the number of thefree blocks increases, the controller 4 may change the write mode of thewrite data to the SLC mode if the SLC write is enabled.

FIG. 5 shows an example in which the host 2 sends one set of the SLCwrite disable command and the SLC write enable command to the SSD 3.When there are a plurality of target periods, the host 2 may send two ormore sets of the SLC write disable command and the SLC write enablecommand to the SSD 3.

With reference to FIGS. 7A and 7B, it will be described an example ofchanges in the number of the free blocks and the write performance. FIG.7A is a graph showing an example of changes in the number of the freeblocks and the write performance in a comparative example where the SSD3 sets a write mode. Assume that the SSD 3 first selects the SLC mode asa write mode. At first, the write performance is high, but the number ofthe free blocks decreases. As the write operation proceeds, the numberof the free blocks decreases. When the number of the free blocks becomesequal to or smaller than a predetermined number, the write operationcannot be executed in the SLC mode, with the result that the write modeis changed to the TLC mode, and the write performance is lowered.Therefore, even though the host 2 then desires a write operation in theSLC mode, the write operation in the SLC mode is not executed when thehost desires the write operation.

FIG. 7B is a graph showing an example of changes in the number of thefree blocks and the write performance in the first embodiment. If theSSD 3 receives no instruction from the host 2, the SSD 3 selects the SLCmode as a write mode. As in the comparative example, the writeperformance is first high, but the number of the free blocks suddenlydecreases. The host 2 sends the SLC write disable command to the SSD 3at a certain point in time. After this point in time, the write mode isset to the TLC mode. Thus, the write performance lowers, but the numberof the free blocks decreases gradually. The host 2 sends the SLC writeenable command to the SSD 3 at the start of the target period or a timeimmediately before the target period. Since the SSD 3 sets the writemode to the SLC mode upon receiving the SLC write enable command, theSSD 3 can execute the write operation in the SLC mode in the targetperiod.

FIG. 8 is a flowchart showing another example of the write operation ofthe host 2 in the storage system 1 according to the first embodiment. Inthe example shown in FIG. 5 , the host 2 sets the SLC write disable timeand the SLC write enable time. In advance, and sends the SLC disablecommand and the SLC enable command to the SSD 3 at corresponding times.As shown in FIG. 8 , however, the host 2 may not decide the times inadvance.

In S140, the host 2 sets the SLC write disable/enable threshold value ofan operation parameter. For example, 60% of the use rate of the CPUincluded in the host 2 may be used as the threshold value of theoperation parameter. Since the host 2 can determine that the load of anapplication is high when the use rate exceeds 60%, the host 2 may enablethe SLC write and increase the data write speed to improve the userexperience. When the use rate falls below 60%, the host 2 may disablethe SLC write and decrease the speed of the write.

In S142, the host 2 determines whether the operation parameter is belowthe threshold value, i.e. the use rate is 60% or less. If the host 2determines that the use rate is below the threshold value (YES in $142),the host sends the SLC write disable command to the SSD 3 in S144. AfterS144, the host 2 may send the write command to the SSD 3 if there isdata to be written.

After S144 or when the host 2 determines in S142 that the use rate isnot below the threshold value (NO in S142), the host 2 determines inS146 whether the operation parameter is above the threshold value, i.e.the use rate is higher than 60%. If the host 2 determines that the userate is above the threshold value (YES in S146), the host 2 sends theSLC write enable command to the SSD 3 in S148. The host 2 sends thewrite command to the SSD 3 in S150. Note that the operation in S150 isexecuted when there is data to be written. Thus, the host 2 may executethe operation in S150 a plurality of times or may not execute theoperation at all.

If the host 2 determines in S146 that the use rate is not above thethreshold value (NO in S146), the host 2 executes the operation in S142again.

As described above, the host 2 determines whether it is the SLC writedisable/enable time based on the operation of the host 2 at any time,and sends the SLC write disable/enable command to the SSD 3 based on aresult of the determination. The host 2 can set the write mode of theSSD 3 to the SLC write mode at a desired Liming.

Upon receiving the SLC write command from the host 2, the SSD 3determines a type of the command (SLC write disable command or SLC writeenable command) and executes the same operation as shown in FIG. 6 .

As has been described above, according to the first embodiment, thewrite operation can be executed in the SLC mode during the targetperiod.

Other embodiments will be described. In the descriptions of the otherembodiments, the same components as those of the first embodiment willbe denoted by the same reference numerals and their detaileddescriptions will be omitted. The same drawings as those of the firstembodiment are not shown.

SECOND EMBODIMENT

in the first embodiment, upon receiving the SLC write enable command,the SSD 3 executes the write operation in the SLC mode until it receivesthe SLC write disable command. In the second embodiment, the executionof write operation in the SLC mode is restricted. More specifically, inthe second embodiment, the host 2 sets a target size of data to bewritten by a write operation in the SLC mode (hereinafter referred to asan SLC writable size) and stops the write operation in the SLC mode ifthe size of data written in the SLC mode (hereinafter referred to as anSLC write data size) exceeds the SLC writable size.

FIG. 9 is a flowchart showing an example of the write operation of thehost 2 in the storage system 1 according to the second embodiment. FIG.10 is a flowchart showing an example of the write operation of the SSD 3in the storage system 1 according to the second embodiment.

As shown in FIG. 9 , the host 2 sets the target period, the SLC writedisable time, the SLC write enable time, and the SLC writable size inS102A.

In 3104, the host 2 determines whether a current time is the SLC writedisable time. If the host 2 determines that the current time is not theSLC write disable time (NO in S104), the host 2 repeats thedetermination in S104 until the SLC write disable time.

If the host 2 determines that the current time is the SLC write disabletime (YES in S104), the host 2 sends the SLC write disable command tothe SSD 3 in S106. The host 2 may send the write command to the SSD 3after S106.

After S106, the host 2 determines in S108 whether a current time is theSLC write enable time. If it is not the SLC write enable time (NO inS108), the host 2 repeats the determination in S108 until the SLC writeenable time.

If the host 2 determines that the current time is the SLC write enabletime (YES in S108), the host 2 sends an SLC writable size information tothe SSD 3 in S202. The host 2 may send the SLC writable size informationas an SLC writable size designation command. Since the host 2 manages asize of data to be written in the SLC mode, the host 2 can determine anSLC writable size in accordance with the size of data.

After S202, the host 2 sends the SLC write enable command to the SSD 3in 3110. The host 2 sends the write command to the SSD 3 in 3112 andends the operation. Note that the operation in S112 is executed whenthere is data to be written. Thus, the host 2 may execute the operationin S112 a plurality of times or may not execute the operation in S112 atall.

Note that the order of sending the SLC writable size designation commandand the SLC write enabled command may be reversed. Instead of sendingthe SLC writable size designation command and the SLC write enablecommand separately, they can be sent simultaneously. For example, theSLC writable size may be included in the parameter of the SLC writeenable command.

In the SSD 3, as shown in FIG. 10 , upon receiving the SLC write disablecommand from the host 2 in S122, the controller 4 sets the write mode tothe TLC mode in S124. The controller 4 receives the SLC writable sizeinformation from the host 2 in S212. Upon receiving the SLC write enablecommand from the host 2 in S126, the controller 4 determines in S128whether the free block pool 116 includes a sufficient number of the freeblocks 118.

When the host 2 changes a method of sending the SLC writable sizedesignation command and the SLC write enable command (e.g. simultaneoussending or separate sending, and the order of sending in the case ofseparate sending) from the example shown in FIG. 9 , the SSD 3 changes amethod of receiving the SLC writable size designation command and theSLC write enable command in accordance with the change of the sendingmethod.

If the controller 4 determines that the free block pool 116 does notinclude a sufficient number of the free blocks (NO in S128), thecontroller 4 returns an error signal to the host 2 in S130. After S130,the controller 4 ends the operation.

If the controller 4 determines that the free block pool 116 includes asufficient number of the free blocks (YES in S128), the controller 4sets the write mode of the write data to the SLC mode in S132. Thecontroller 4 returns information indicating that the write mode has beenset to the SLC mode to the host 2 in S134.

Upon receiving the write command from the host 2 in 3135, the controller4 writes the data into the SLC write destination block 102 of the NANDflash memory 5 in S136, as shown in FIG. 2 . If the controller 4receives no write command from the host 2, the controller 4 does notexecute the operations in S135 and S136.

The controller 4 determines in S214 whether the SLC write data sizeexceeds the SLC writable size or whether there are no sufficient freeblocks in the free block pool 116. If the controller 4 determines thatthe SLC write data size does not exceed the SLC writable size and thereare a sufficient number of the free blocks in the free block pool 116(NO in S214), the controller 4 continues the operations in S135, 3136,and S214.

If the controller 4 determines that the SLC write data size exceeds theSLC writable size or there are no sufficient free blocks in the freeblock pool 116 (YES in S214), the controller 4 sets the write mode tothe TLC mode in S216 even if the controller 4 does not receive a modeset command from the host 2. As shown in FIG. 3 , the controller 4writes the data into the TLC write destination block 126 of the NANDflash memory 5 in S21 and ends the operation.

FIG. 11A is a graph showing an example of changes in the number of thefree blocks and the write performance in a comparative example where theSSD 3 sets a write mode. FIG. 11A corresponds to FIG. 7A.

FIG. 11B is a graph showing an example of changes in the number of thefree blocks and the write performance in the second embodiment. As inthe first embodiment, the write performance is improved during theperiod desired by a user. In addition, according to the secondembodiment, when the SLC write data size exceeds the SLC writable sizeor when there are no sufficient free blocks in the free block pool 116,the host 2 stops the write operation in the SLC mode and then executesthe write operation in the TLC mode. After that, the write performanceis deteriorated, but the number of the free blocks decreases gradually.FIG. 11B shows an example where the host 2 stops the write operation inthe SLC mode because the SLC write data size exceeds the SLC writablesize.

THIRD EMBODIMENT

Like the second embodiment, the third embodiment relates to restrictionson the execution of the write operation in the SLC mode. In the thirdembodiment, the host 2 sets a target period during which the host 2desires to a write operation in the SLC mode (hereinafter referred to asSLC writable time). The host 2 stops the write operation in the SLC modewhen a time for writing the data in the SLC mode (hereinafter referredto as SLC data write time) exceeds the SLC writable time.

FIG. 12 is a flowchart showing an example of the write operation of thehost 2 in the storage system 1 according to the third embodiment. FIG.13 is a flowchart showing an example of the write operation of the SSD 3in the storage system 1 according to the third embodiment.

As shown in FIG. 12 , the host 2 sets the target period, the SLC writedisable time, the SLC write enable time, and the SLC writable time inS102B.

In S104, the host 2 determines whether a current time is the SLC writedisable time. If the host 2 determines that the current time is not theSLC write disable time (NO in S104), the host 2 repeats thedetermination in S104 until the SLC write disable time.

If the host 2 determines that the current time is the SLC write disabletime (YES in S104), the host 2 sends the SLC write disable command tothe SSD 3 in S106. The host 2 may send the write command to the SSD 3after S106 if there is data to be written.

After S106, the host 2 determines in S108 whether a current time is theSLC write enable time. If it is not the SLC write enable time (NO inS108), the host 2 repeats the determination in S108 until the SLC writeenable time.

If the host 2 determines that the current time is the SLC write enabletime (YES in S108), the host 2 sends the SLC writable time informationto the SSD 3 in S302. The host 2 may send the SLC writable timeinformation as the SLC writable time designation command. Since the host2 manages for what seconds data is to be written in the SLC mode, thehost 2 can determine the SLC writable time in accordance with the numberof seconds.

After S302, the host 2 sends the SLC write enable command to the SSD 3in S110. The host 2 sends the write command to the SSD 3 in S112 andends the operation. Note that the operation in S112 is executed whenthere is data to be written. Thus, the host 2 may execute the operationin S112 a plurality of times or may not execute the operation in S112 atall.

Note that the order of sending the SLC writable time designation commandand the SLC write enable command may be reversed. Instead of sending theSLC writable time designation command and the SLC write enable commandseparately, they can be sent simultaneously. For example, the SLCwritable time information may be included in the parameter of the SLCwrite enable command.

In the SSD 3, as shown in FIG. 13 , upon receiving the SLC write disablecommand from the host 2 in S122, the controller 4 sets the write mode tothe TLC mode in S124. Upon receiving the write data from the host 2, thecontroller 4 writes the data into the TLC write destination block 126 ofthe NAND flash memory 5 as shown in FIG. 3 . After that, the controller4 receives the SLC writable time information from the host 2 in S312.Upon receiving the SLC write enable command from the host 2 in S126, thecontroller 4 determines in S128 whether the free block pool 116 includesa sufficient number of the free blocks 118.

When the host 2 changes a method of sending the SLC writable timedesignation command and the SLC write enable command from the exampleshown in FIG. 12 , the SSD 3 changes a method of receiving the SLCwritable time designation information and the SLC write enable commandin accordance with the change of the sending method.

If the controller 4 determines that the free block pool 116 does notinclude a sufficient number of the free blocks (NO in S128), thecontroller 4 returns an error signal to the host. 2 in S130. After S130,the controller 4 ends the operation.

If the controller 4 determines that the free block pool 116 includes asufficient number of the free blocks (YES in S128), the controller 4sets the write mode of the write data to the SLC mode in S132 even ifthe controller 4 does not receive a mode set command from the host 2.The controller 4 returns information indicating that the write mode hasbeen set to the SLC mode to the host in S134.

Upon receiving the write command from the host 2 in S135, the controller4 writes the data into the SLC write destination block 102 of the NANDflash memory 5 in S136, as shown in FIG. 2 . If the controller 4receives no write command from the host 2, the controller 4 does notexecute the operations in S135 and S136.

The controller 4 determines in S314 whether the SLC data write timeexceeds the SLC writable time or whether there are no sufficient freeblocks in the free block pool 116. If the controller 4 determines thatthe SLC data write time does not exceed the SLC writable time and thereare a sufficient number of the free blocks in the free block pool 116(NO in S314), the controller 4 continues the operations in S135, S136,and S314.

If the controller 4 determines that the SLC data write time exceeds theSLC writable time or there are no sufficient free blocks in the freeblock pool 116 (YES in S314), the controller 4 sets the write mode tothe TLC mode in S216. The controller 4, as shown in FIG. 3 , writes thedata into the TLC write destination block 126 of the NAND flash memory 5in S218 and ends the operation.

According to the third embodiment, when the SLC data write time exceedsthe SLC writable time or when there are no sufficient free blocks in thefree block pool 116, the host 2 stops the write operation in the SLCmode and then executes the write operation in the TLC mode. In thesecond embodiment, the host 2 stops the write operation in the SLC modebased on the SLC write data size instead of the SLC data write time. Theforegoing example of changes in the number of the free blocks and thewrite performance in the third embodiment is not shown because it is thesame as the example of changes in the second embodiment shown in FIGS.11A and 11B. The second and third embodiments are different from eachother in a criterion of determining a time when the write performancelowers, but the SLC write data size and the SLC data write time arerelated to each other. Therefore, the second and third embodiments bringabout substantially the same advantages.

The operation of the host 2 in each of the second and third embodimentsis based on the operation of the host 2 in the first embodiment shown inFIG. 5 , but may be based on the operation of the host 2 in themodification to the first embodiment shown in FIG. 8 . In the lattercase, S202 of sending the SLC writable size to the SSD 3 (FIG. 9 ) orS302 of sending the SLC writable time to the SSD 3 (FIG. 12 ) isexecuted immediately before S148 of sending the SLC write enable commandto the SSD 3 (FIG. 8 ).

FOURTH EMBODIMENT

The second and third embodiments relate to restrictions on the executionof the write operation when the SLC write is enabled. Next is adescription of a fourth embodiment in which the GC/compaction isexecuted when the SLC write is disabled to generate the free blocks andrecover the number of the free blocks.

FIG. 14 is a flowchart showing an example of the write operation of theSSD 3 in the storage system 1 according to the fourth embodiment.

The operation of the host 2 may be any of the operation of the firstembodiment shown in FIG. 5 , that of the modification to the firstembodiment shown in FIG. 8 , that of the second embodiment shown in FIG.9 , and that of the third embodiment shown in FIG. 12 .

As shown in FIG. 14 , upon receiving the SLC write disable command fromthe host 2 in S122, the controller 4 sets the write mode to the TLC modein S124. Then, upon receiving the write data from the host 2, thecontroller 4 writes the data into the TLC write destination block 126 ofthe NAND flash memory 5.

After that, as shown in FIG. 3 , the controller 4 executes theGC/compaction to generate the free blocks in S402. The GC/compaction maybe exccuted in an idle period in which no I/O command such as the writecommand and the read command is sent from the host 2. If, however, thereis no idle period, the execution of the I/O command from the host 2 maybe delayed to execute the GC/compaction preferentially. The priority ofthe GC/compaction may be used as an index indicating which of theGC/compaction and the I/O command from a host is preferentiallyexecuted. The priority of the GC/compaction may be determined by the SSD3 or may be designated by the host 2.

After S402, the controller 4 receives the SLC write enable command fromthe host 2 in S126, the controller 4 sets the write mode to the SLC modein S132 and then returns information indicating that the write mode hasbeen set to the SLC mode to the host 2 in S134.

The controller 4 receives the write command from the host 2 in S135. Thecontroller 4 writes the data into the SLC write destination block 102 ofthe NAND flash memory 5 in S136, as shown in FIG. 2 . If the controller4 receives no write command from the host 2, the controller 4 does notexecute the operations in S135 and S136.

After S136, the controller 4 determines in S404 whether the free blockpool 116 includes a sufficient number of the free blocks 118.

If the controller 4 determines that the free block pool 116 includes asufficient number of the free blocks (YES in S404), the controller 4continues the operations in S135, S136, and S404.

If the controller 4 determines that the free block pool 116 does notinclude a sufficient number of the free blocks (NO in S404), thecontroller 4 sets the write mode to the TLC mode in S406. Upon receivingthe write command from the host 2 in S407, the controller 4 writes thedata into the TLC write destination block 126 of the NAND flash memory 5in S408 and ends the operation.

FIG. 15A is a graph showing an example of changes in the number of thefree blocks and the write performance in the first embodiment. FIG. 15Acorresponds to FIG. 7B.

FIG. 15B is a graph showing an example of changes in the number of thefree blocks and the write performance in the fourth embodiment. In thefourth embodiment, upon receiving the SLC write disable command, the SSD3 executes the GC/compaction to increase the number of the free blocks.The number of the free blocks at the start of the target period islarger than that in the first embodiment. Even though the host 2 desireshigh write performance for a long period, the free blocks remain in thefree block pool 116 until the end of the period, with the result thatthe write operation can be executed in the SLC mode.

However, in the first embodiment in which no GC/compaction is executed,even though the SSD 3 receives the SLC write disable command, the SSD 3executes the write operation in the TLC mode so that the number of thefree blocks are decreased gradually, as shown in FIG. 15A. Thus, whenthe host 2 desires high write performance for a long period, the numberof the free blocks becomes equal to or smaller than a predeterminednumber in the middle of the period. After that, the write operation maynot be executed in the SLC mode.

In the write operation of the SSD 3 shown in FIG. 14 , the SSD 3determines an execution time of the GC/compaction. However, the fourthembodiment can be modified such that the host 2 sets the execution timeof the GC/compaction.

FIG. 16 is a flowchart showing an example of the write operation of thehost 2 in the storage system 1 according to a modification of the fourthembodiment.

FIG. 17 is a flowchart showing an example of the write operation of theSSD 3 in the storage system 1 according to the modification to thefourth embodiment.

As shown in FIG. 16 , the host 2 sets the target period, the SLC writedisable time, and the SLC write enable time in S102.

In 3104, the host 2 determines whether a current time is the SLC writedisable time. If the host 2 determines that the current time is not theSLC write disable time (NO in S104), the host 2 repeats thedetermination in S104 until the SLC write disable time.

If the host 2 determines that the current time is the SLC write disabletime (YES in S104), the host 2 sends the SLC write disable command tothe SSD 3 in S106. The host 2 may send the write command to the SSD 3after S106 if there is data to be written.

After S106, the host 2 sends a GC/compaction command to the SSD 3 inS412. The host 2 sends the GC/compaction command to the SSD 3 at a timewhen the host 2 does not send an I/O command to the SSD 3. TheGC/compaction command may include the priority of the GC/compaction. Thehost 2 can control the priority of the GC/compaction by sending theGC/compaction command including the priority to the SSD 3, with theresult that the host 2 can also control the degree of degradation of thewrite performance. Thus, the host 2 can control the degradation of thewrite performance due to the GC/compaction.

In 3108, the host 2 determines whether a current time is the SLC writeenable time. If the host 2 determines that the current time is not theSLC write enable time, the host 2 repeats the determination in S108until the SLC write enable time.

If the host 2 determines that the current time is the SLC write enabletime (YES in S108), the host 2 sends the SLC write enable command to theSSD 3 in 3110. The host 2 sends the write command to the SSD 3 in S112and ends the operation. Note that the operation in S112 is executed whenthere is data to be written. Thus, the host 2 may execute the operationin S112 a plurality of times or may not execute the operation in S112 atall.

The operation in FIG. 16 is based on the operation of the host 2 in thefirst embodiment shown in FIG. 5 , but may be based on the operation ofthe host 2 in the modification to the first embodiment shown in FIG. 8 .In the latter case, S412 of sending the GC/compaction command to the SSD3 is executed between S144 of sending the SLC write disable command tothe SSD 3 and S148 of sending the SLC write enable command to the SSD 3,which are shown in FIG. 8 .

In the SSD 3, as shown in FIG. 17 , upon receiving the SLC write disablecommand from the host 2 in S122, the controller 4 sets the write mode tothe TLC mode in S124. Then, upon receiving the write data from the host2, the controller 4 writes the data into the TLC write destination block126 of the NAND flash memory 5 as shown in FIG. 3 . After that, uponreceiving the GC/compaction command in S416, the controller 4 executesthe GC/compaction in S418. When the controller 4 receives the priorityof the GC/compaction together with the GC/compaction command, thecontroller 4 executes the GC/compaction in accordance with the receivedpriority in S418.

After S418, upon receiving the SLC write enable command from the host 2in S126, the controller 4 sets the write mode to the SLC mode in S132and then returns information indicating that the write mode has been setto the SLC mode to the host 2 in S134.

Upon receiving the write command from the host 2 in S135, the controller4 writes the data into the SLC write destination block 102 of the NANDflash memory 5 in S136, as shown in FIG. 2 . If the controller 4receives no write command from the host 2, the controller 4 does notexecute the operations in S135 and S136.

After S136, the controller 4 determines in S422 whether the free blockpool 116 includes a sufficient number of the free blocks 118.

If the controller 4 determines that the free block pool 116 includes asufficient number of the free blocks (YES in S422), the controller 4continues the operations in S135, S136, and S422.

If the controller 4 determines that the free block pool 116 does notinclude a sufficient number of the free blocks (NO in S422), thecontroller 4 sets the write mode to the TLC mode in S424. Upon receivingthe write command from the host 2 in S425, the controller 4 writes thedata into the TLC write destination block 126 of the NAND flash memory 5in 3426 and ends the operation.

FIFTH EMBODIMENT

The fourth embodiment relates to the start of the GC/compaction. If theGC/compaction is executed more than necessary, the write performance isdeteriorated more than necessary. Next is a description of a fifthembodiment in which the stop of the GC/compaction is controlled.

FIG. 18 is a flowchart showing an example of the write operation of thehost 2 in the storage system 1 according to the fifth embodiment. FIG.19 is a flowchart showing an example of the write operation of the SSD 3in the storage system 1 according to the fifth embodiment.

As shown in FIG. 18 , the host 2 sees the target period, the SLC writedisable time, the SLC write enable time, and a target capacity of thefree blocks in S102C.

In S104, the host 2 determines whether a current time is the SLC writedisable time. If the host 2 determines that the current time is not theSLC write disable time (NO in S104), the host 2 repeats thedetermination in S104 until the SLC write disabled time.

If the host 2 determines that the current time is the SLC write disabletime (YES in S104), the host 2 sends the target capacity information ofthe free blocks to the SSD 3 in S502. The host 2 may send the targetcapacity information as a target capacity designation command. Thetarget capacity of the free blocks is the number of the free blocks 118allocated to the free block pool 116 at the end of the GC/compaction orat the start of the target period. In other words, the target capacityof the free blocks is an index to determine when the GC/compaction is tobe stopped. The target capacity of the free blocks is so determined thata sufficient number of the free blocks are allocated to the free blockpool 116 at the end of the target period.

After S502, the host 2 sends the SLC write disable command to the SSD 3in 3106. The host 2 may send the write command to the SSD 3 after S106if there is data to be written.

After S106, the host 2 determines in S108 whether a current time is theSLC write enable time. If the host 2 determines that the current time isnot the SLC write enable time, the host 2 repeats the determination inS108 until the SLC write enable time.

If the host 2 determines that the current time is the SLC write enabletime (YES in S106), the host 2 sends the SLC write enable command to theSSD 3 in S110. The host 2 sends the write command to the SSD 3 in S112and ends the operation. Note that the operation in S112 is executed whenthere is data to be written. Thus, the host 2 may execute the operationin S112 a plurality of times or may not execute the operation in S112 atall.

Note that the order of sending the target capacity information and theSLC write disable command may be reversed. Instead of sending the targetcapacity information and the SLC write disable command separately, theycan be sent simultaneously. For example, the target capacity informationmay be included in the parameter of the SLC write disable command.

The operation in FIG. 18 is based on the operation of the host 2 in thefirst embodiment shown in FIG. 5 , but may be based on the operation ofthe host 2 in the modification to the first embodiment shown in FIG. 8 .In the latter case, S502 of sending the target capacity information tothe SSD 3 is executed before S144 of sending the SLC write disablecommand to the SSD 3 shown In FIG. 8 .

In the SSD 3, as shown in FIG. 19 , upon receiving the target capacityinformation of the free blocks from the host 2 in S504, the controller 4divides the target capacity by the size of the block of data to bewritten in the SLC mode to calculate a target number of the free blocksrequired to achieve the target capacity of the free blocks in S506.

After S506, upon receiving the SLC write disable command from the host 2in S122, the controller 4 sets the write mode to the TLC mode in S124.Then, when the controller 4 receives the write data from the host 2, thecontroller 4 writes the data into the TLC write destination block 126 ofthe NAND flash memory 5 as shown in FIG. 3 .

When the host 2 changes a method of sending the target capacityinformation and the SLC write disable command from the example shown inFIG. 18 , the SSD 3 changes a method of receiving the target capacityinformation and the SLC write disable command in accordance with thechange of the sending method.

After S124, the controller 4 determines in S508 whether the number ofthe free blocks 118 which is allocated to the free block pool 116exceeds the target number of the free blocks.

When the controller 4 determines that the number of the free blocks 118does not exceed the target number of the free blocks (NO in S508), thecontroller 4 executes the GC/compaction in S512. The controller 4executes the operation of S512 until the controller 4 determines thatthe number of the free blocks 118 exceeds the target number of the freeblocks. That is, the controller 4 stops the GC/compaction when thenumber of the free blocks 113 exceeds the target number of the freeblocks.

When the controller 4 determines that the number of the free blocks 118exceeds the target number of the free blocks (YES in S508), uponreceiving the SLC write enable command from the host 2 in S126, thecontroller 4 sets the write mode to the SLC mode in S132. The controller4 returns information indicating that the write mode has been set to theSLC mode to the host 2 in S134.

Upon receiving the write command from the host 2 in S135, the controller4 writes the data into the SLC write destination block 102 of the NANDflash memory 5 in S136 as shown in FIG. 2 and ends the operation. If thecontroller 4 receives no write command from the host 2, the controller 4does not execute the operations in S135 and S136.

FIG. 20A is a graph showing an example of changes in the number of thefree blocks and the write performance in the fourth embodiment shown inFIG. 15B. FIG. 20B is a graph showing an example of changes in thenumber of the free blocks and the write performance in the fifthembodiment.

As shown in FIG. 20A, in the fourth embodiment, when the SSD 3 receivesthe SLC write disable command, the controller 4 executes theGC/compaction to increase the number of the free blocks. During theGC/compaction, however, the SSD 3 stands by for the write operation ofdata from the host 2 and thus the write performance is degraded.

According to the fifth embodiment, however, as shown in FIG. 20B, whenthe SSD 3 receives the target capacity information from the host 2together with the SLC write disable command and the target capacity ofthe free blocks is achieved, the controller 4 stops the GC/compaction.Thus, the GC/compaction is not executed more than necessary. The periodof write performance degradation due to the GC/compaction is shorterthan that in the fourth embodiment. Since the execution time of theGC/compaction is short, the degree of wear-out of the blocks does notincrease.

SIXTH EMBODIMENT

In the fifth embodiment, the host 2 sets the target capacity of the freeblocks and accordingly the SSD 3 determines the end time of theGC/compaction. Next is a description of a sixth embodiment in which thehost 2 designates a target execution time of the GC/compaction andaccordingly the SSD 3 determines the end time the GC/compaction.

FIG. 21 is a flowchart showing an example of the write operation of thehost 2 in the storage system 1 according to the sixth embodiment. FIG.22 is a flowchart showing an example of the write operation of the SSD 3in the storage system 1 according to the sixth embodiment.

As shown in FIG. 21 , the host 2 sets the target period, the SLC writedisable time, the SLC write enable time, and the target execution timeof the CG/compaction in S102D.

In S104, the host 2 determines whether a current time is the SLC writedisable time. If the host 2 determines that the current time is not theSLC write disable time, the host 2 repeats the determination in S104until the SLC write disable time.

If the host 2 determines that the current time is the SLC write disabletime (YES in S104), the host 2 sends the target execution timeinformation of the CG/compaction to the SSD 3 in S602. The host 2 maysend the target execution time information as a target execution timedesignation command. The target execution time is determined, forexample, from a time that allows performance degradation due to theCG/compaction during the SLC write disable period.

After S602, the host 2 sends the SLC write disable command to the SSD 3in S106. The host 2 may send the write command to the SSD 3 after S106if there is data to be written.

After S106, the host 2 determines in S108 whether a current time is theSLC write enable time. If the host 2 determines that the current time isnot the SLC write enable time, the host 2 repeats the operation in S108until the SLC write enable time.

If the host 2 determines that the current time is the SLC write enabletime (YES in S108), the host 2 sends the SLC write enable command to theSSD 3 in S110. The host 2 sends the write command to the SSD 3 in S112and ends the operation. Note that the operation in S112 is executed whenthere is data to be written. Thus, the host 2 may execute the operationin S112 a plurality of times or may not execute the operation in S112 atall.

Note that the order of sending the target execution time information andthe SLC write disable command may be reversed. Instead of sending thetarget execution time information and the SLC write disable commandseparately, they can be sent simultaneously. For example, the targetexecution time information may be included in the parameter of the SLCwrite disable command.

The operation in FIG. 21 is based on the operation of the host 2 in thefirst embodiment shown in FIG. 5 , but may be based on the operation ofthe host 2 in the modification to the first embodiment shown in FIG. 3 .

In the latter case, S602 of sending the target execution timeinformation to the SSD 3 is executed before S144 of sending the SLCwrite disable command to the SSD 3 shown in FIG. 8 .

In the SSD 3, as shown in FIG. 22 , the controller 4 receives the targetexecution time information of the CG/compaction from the host 2 in S602.

After S602, upon receiving the SLC write disable command from the host 2in S122, the controller 4 sets the write mode to the TLC mode in S124.Then, when the controller 4 receives the write data from the host 2, thecontroller 4 writes the data into the TLC write destination block 126 ofthe NAND flash memory 5 as shown in FIG. 3 .

When the host 2 changes a method of sending the target execution timeinformation and the SLC write disable command from the example shown inFIG. 21 , the SSD 3 changes a method of receiving the target executiontime information and the SLC write disable command in accordance withthe change of the sending method.

After S124, the controller 4 determines in S604 whether a CG/compactionexecution time exceeds the target execution time.

When the controller 4 determines that the CG/compaction execution timedoes not exceed the target execution time (NO in S604), the controller 4executes the GC/compaction in S606. The controller 4 executes theoperation of S604 until the controller 4 determines that theCG/compaction execution time exceeds the target execution time. That is,the controller 4 stops the GC/compaction when the CG/compactionexecution time exceeds the target execution time.

When the controller 4 determines that the CG/compaction execution timeexceeds the target execution time (YES in S604) and receives the SLCwrite enable command from the host 2 in 3126, the controller 4 sets thewrite mode to the SLC mode in S132. The controller 4 returns informationindicating that the write mode has been set to the SLC mode to the host2 in S134.

Upon receiving the write command from the host 2 in S135, the controller4 writes the data into the SLC write destination block 102 of the NANDflash memory 5 in S136 as shown in FIG. 2 and ends the operation. If thecontroller 4 receives no write command from the host 2, the controller 4does not execute the operations in S135 and S136.

FIG. 23A is a graph showing an example of changes in the number of thefree blocks and the write performance in the fourth embodiment shown inFIG. 15B. FIG. 23B is a graph showing an example of changes in thenumber of the free blocks and the write performance in the sixthembodiment.

As shown in FIG. 23A, in the fourth embodiment, when the SSD 3 receivesthe SLC write disable command, the controller 4 executes theGC/compaction to increase the number of the free blocks. During theGC/compaction, however, the SSD 3 stands by for the write operation ofdata from the host 2 and thus the write performance is degraded.

According to the sixth embodiment, however, as shown In FIG. 23B, whenthe SSD 3 receives the target execution time information of theCG/compaction from the host 2 together with the SLC write disablecommand, if the CG/compaction execution time reaches the targetexecution time, the controller 4 stops the GC/compaction. Thus, theGC/compaction is not executed more than necessary. The period of writeperformance degradation due to the GC/compaction is shorter than that inthe fourth embodiment. Since the time for executing the GC/compaction isshort, the degree of wear-out of the blocks does not increase.

In the fifth and sixth embodiments, the host 2 sets the target capacityof the free blocks and the target execution time of the GC/compactionfor each SLC write disable command, but may designate the targetcapacity and the target execution time only when they are changed. Inthis case, the SSD 3 may store the target capacity information andtarget execution time information. If the host 2 does not designatethem, the SSD 3 may use the last stored target capacity information andtarget execution time information. In addition, the same target capacityand the same target execution time may be used each time. In this case,the host 2 may send the target capacity information and the targetexecution time information at the time of first sending of the SLC writedisable command.

SEVENTH EMBODIMENT

In the fifth or sixth embodiment, the host 2 sets the target capacity ofthe free blocks or the target execution time of the GC/compaction, andthe SSD. 3 determines the end time of the GC/compaction based on thedesignated target capacity or target execution time, thereby shorteninga period during which the write performance is degraded. In the fifth orsixth embodiment, however, the first half of the period from thereception or the SLC write disable command to the reception of the SLCwrite enable command is a period during which the GC/compaction isexecuted, and the second half thereof is a period during which noGC/compaction is executed. Next is a description of a seventh embodimentin which the GC/compaction is executed with the priority based on thedesignation information of the host 2 during the period from thereception of the SLC write disable command to the reception of the SLCwrite enable command.

FIG. 24 is a flowchart showing an example of the write operation of thehost 2 in the storage system 1 according to the seventh embodiment. FIG.25 is a flowchart showing an example of the write operation of the SSD 3in the storage system 1 according to the seventh embodiment.

As shown in FIG. 24 , the host 2 sets the target period, the SLC writedisable time, the SLC write enable time, and a write performancedegradation acceptable value in S102E.

In S104, the host 2 determines whether a current time is the SLC writedisable time. If the host 2 determines that the current time is not theSLC write disable time (NO in S104), the host 2 repeats thedetermination in S104 until the SLC write disable time.

If the host 2 determines that the current time is the SLC write disabletime (YES in S104), the host 2 sends the write performance degradationacceptable value to the SSD 3 in S702.

The host 2 may send the write performance degradation acceptable valueas an acceptable value designation command. The write performance can berepresented by guaranteed throughput (bytes/second), latency (seconds)and the like. The lower value of the guaranteed throughput(bytes/second) and the upper value of the latency (seconds) are sent tothe SSD 3 as acceptable values of the degradation.

After S702, the host 2 sends the SLC write disable command to the SSD 3in 3106.

After S106, the host 2 determines in S108 whether a current time is theSLC write enable time. If the host 2 determines that the current time isnot the SLC write enable time (NO in S108), the host 2 repeats theoperation in S108 until the SLC write enable time.

If the host 2 determines that the current time is the SLC write enabletime (YES in S108), the host 2 sends the SLC write enable command to theSSD 3 in S110. The host 2 sends the write command to the SSD 3 in S112and ends the operation. Note that the operation in S112 is executed whenthere is data to be written. Thus, the host 2 may execute the operationin S112 a plurality of times or may not execute it at all.

Note that the order of sending the write performance degradationacceptable value and the SLC write disable command may be reversed.Instead of sending the write performance degradation acceptable valueand the SLC write disable command separately, they can be sentsimultaneously. For example, the write performance degradationacceptable value may be included in the parameter of the SLC writedisable command.

The operation in FIG. 24 is based on the operation of the host 2 in thefirst embodiment shown in FIG. 5 , but may be based on the operation ofthe host 2 in the modification to the first embodiment shown in FIG. 3 .

In the latter case, S702 of sending the write performance degradationacceptable value to the SSD 3 is executed before S144 of sending the SLCwrite disable command to the SSD 3 shown in FIG. 8 .

In the SSD 3, as shown in FIG. 25 , the controller 4 receives the writeperformance degradation acceptable value from the host 2 in S704.

After S704, upon receiving the SLC write disable command from the host 2in S122, the coni-roller 4 sets the write mode to the TLC mode in S124.Then, when the controller 4 receives the write data from the host 2, thecontroller 4 writes the data into the TLC write destination block 126 ofthe NAND flash memory 5 as shown in FIG. 3 .

When the host 2 changes a method of sending the write performancedegradation acceptable value and the SLC write disable command from theexample shown in FIG. 24 , the SSD 3 also changes a method of receivingthe write performance degradation acceptable value and the SLC writedisable command in accordance with the change of the sending method.

After S124, the controller 4 sets the priority of the GC/compaction inS706 so that the degree of write performance degradation does not exceedthe acceptable value. As the priority of the GC/compaction increases,the free block generation speed improves, but the write performance isdegraded. As the priority of the GC/compaction lowers, the free blockgeneration speed decreases, but the write performance is not sodegraded. The controller 4 sets the priority of the GC/compaction inaccordance with the write performance degradation acceptable valuedesignated by the host 2.

Unlike in the fifth and sixth embodiments, in the seventh embodiment,the GC/compaction is executed during a period from the reception of theSLC write disable command to the reception of the SLC write enablecommand.

After S706, the controller 4 executes the GC/compaction in S708 inaccordance with the determined priority. As a result, the writeperformance is degraded by the GC/compaction, but the degree of writeperformance degradation falls within the acceptable value.

After 3708, upon receiving the SLC write enable command from the host 2in S126, the controller 4 sets the write mode to the SLC mode in S132and then returns information indicating that the write mode has been setto the SLC mode to the host 2 in S134.

Upon receiving the write command from the host 2 in 3135, the controller4 writes the data into the SLC write destination block 102 of the NANDflash memory 5 in S136, as shown in FIG. 2 . If the controller 4receives no write command from the host 2, the controller 4 does notexecute the operations in S135 and S136.

FIG. 26A is a graph showing an example of changes in the number of thefree blocks and the write performance in the sixth embodiment shown inFIG. 23B. FIG. 26B is a graph showing an example of changes in thenumber of the free blocks and the write performance in the seventhembodiment. As shown in FIG. 26A, in the sixth embodiment, when the SSD3 receives the SLC write disable command, it executes the GC/compactionto increase the number of the free blocks. During the GC/compaction,however, the SSD 3 stands by for the write operation of data from thehost 2 and thus the write performance is degraded. The GC/compaction isexecuted only in the first half of the period from the reception of theSLC write disable command to the reception of the SLC write enablecommand. Thus, the write performance varies between the first half andthe second half of the period from the reception of the SLC writedisable command to the reception of the SLC write enable command.

According to the seventh embodiment, however, the SSD 3 receives thewrite performance degradation acceptable value from the host 2 togetherwith the SLC write disable command. The SSD 3 calculates the priority ofthe GC/compaction according to the degradation acceptable value.Therefore, as shown in FIG. 26B, the GC/compaction is executed inaccordance with the priority during the period from the reception of theSLC write disable command to the reception of the SLC write enablecommand. The write performance is made uniform during the period.

EIGHTH EMBODIMENT

In the seventh embodiment, the write performance can be prevented frombeing degraded; however, it may be likely that the number of the freeblocks allocated to the free block pool 116 does not reach a desirednumber at the end of the GC/compaction. Next is a description of aneighth embodiment in which the degradation of write performance can beminimized while a desired number of the free blocks are generated.

FIG. 27 is a flowchart showing an example of the write operation of thehost 2 in the storage system 1 according to the eighth embodiment. FIG.28 is a flowchart showing an example of the write operation of the SSD 3in the storage system 1 according to the eighth embodiment.

As shown in FIG. 27 , the host 2 sets the target period, the SLC writedisable time, the SLC write enable time, the target capacity of the freeblocks, and the target execution time of the CG/compaction in S102F.

In S104, the host 2 determines whether a current time is the SLC writedisable time. If the host 2 determines that the current time is not theSLC write disable time (NO in S104), the host 2 repeats thedetermination in S104 until the SLC write disable time.

If the host 2 determines that the current time is the SLC write disabletime (YES in S104), the host 2 sends the target capacity information ofthe free blocks to the SSD 3 in S712. The host 2 may send the targetcapacity information as the target capacity designation command. Thetarget capacity of the free blocks is the capacity described in thefifth embodiment.

After S712, the host 2 sends the target execution time information ofthe GC/compaction to the SSD 3 in S714. The host 2 may send the targetexecution time information as the target execution time designationcommand. The target execution time of the GC/compaction is the timedescribed in the sixth embodiment.

After S714, the host. 2 sends the SLC write disable command to the SSD 3in S106.

After S106, the host 2 determines in S108 whether a current time is theSLC write enable time. If the host 2 determines that the current time isnot the SLC write enable time (NO in S106), the host 2 repeats thedetermination in S108 until the SLC write enable time.

If the host 2 determines that the current time is the SLC write enabletime (YES in S108), the host. 2 sends the SLC write enable command tothe SSD 3 in S110. The host 2 sends the write command to the SSD 3 inS112 and ends the operation. Note that the operation in S112 is executedwhen there is data to be written. Thus, the host 2 may execute theoperation in S112 a plurality of times or may not execute the operationin S112 at all.

Note that the order of sending the target capacity information, thetarget execution time information, and the SLC write disable command maybe changed. Instead of sending the target capacity information, thetarget execution time information, and the SLC write disable commandseparately, they can be sent simultaneously. For example, the targetcapacity information and the target execution time information may beincluded in the parameters of the SLC write disable command.

The operation in FIG. 27 is based on the operation of the host 2 in thefirst embodiment shown in FIG. 5 , but may be based on the operation ofthe host 2 in the modification to the first embodiment shown in FIG. 8 .In the latter case, S712 of sending the target capacity information andS714 of sending the target execution time information are executedbefore S144 of sending the SLC write disable command to the SSD 3 shownin FIG. 8 .

In the SSD 3, as shown in FIG. 28 , the controller 4 receives the targetcapacity information from the host 2 in S722 and receives the targetexecution time information from the host 2 in S723.

After S723, the controller 4 divides the target capacity by the size ofthe block of data to be written in the SLC mode to calculate a targetnumber of the free blocks required to achieve the target capacity of thefree blocks in S724.

After S724, upon receiving the SLC write disable command from the host 2in S122, the controller 4 sets the write mode to the TLC mode in S124.Then, when the controller 4 receives the write data from the host 2, thecontroller 4 writes the data into the TLC write destination block 126 ofthe NAND flash memory 5 as shown in FIG. 3 .

When the host 2 changes a method of sending the target capacityinformation, the target execution time information, and the SLC writedisable command from the example shown in FIG. 27 , the SSD 3 changes amethod of receiving the target capacity information, the targetexecution time information, and the SLC write disable command inaccordance with the sending method.

In S726, the controller 4 sets the priority of the GC/compaction so thatthe number of the free blocks allocated to the free block pool 116reaches the target number of the free blocks. The higher the priority ofthe GC/compaction, the higher the rate of increase in the number of thefree blocks. The lower the priority of the GC/compaction, the lower therate of increase in the number of the free blocks.

After S726, the controller 4 executes the GC/compaction only for thetarget execution time in accordance with the determined priority inS728. Thus, the GC/compaction makes it possible to generate the targetnumber of the free blocks and minimize the degradation of the writeperformance.

After S728, upon receiving the SLC write enable command from the host 2in S126, the controller 4 sets the write mode to the SLC mode in S132.The controller 4 returns information indicating that the write mode hasbeen set to the SLC mode to the host 2 in S134.

Upon receiving the write command from the host 2 in S135, the controller4 writes the data into the SLC write destination block 102 of the NANDflash memory 5 in S136, as shown in FIG. 2 . It the controller 4receives no write command from the host 2, the controller 4 does notexecute the operations in S135 and S136.

FIG. 29A is a graph showing an example of changes in the number of thefree blocks and the write performance in the fourth embodiment shown inFIG. 15B. FIG. 29B is a graph showing an example of changes in thenumber of the free blocks and the write performance in the eighthembodiment.

As shown in FIG. 29A, in the fourth embodiment, the GC/compaction isexecuted to increase the number of the free blocks for the period fromthe reception of the SLC write disable command to the reception of theSLC write enable command. During the GC/compaction, the SSD 3 stands byfor the write operation of data from the host 2 and thus the writeperformance is degraded.

According to the eighth embodiment, as shown in FIG. 29B, the SSD 3receives the target capacity information and the target execution timeinformation together with the SLC write disable command from the host 2.The controller 4 determined the priority of the GC/compaction such thatthe number of the free blocks allocated to the free block pool 116reaches the target number of the free blocks at the end of theGC/compaction. Thus, the GC/compaction makes it possible to generate thetarget number of the free blocks and minimize the degradation of thewrite performance.

NINTH EMBODIMENT

A ninth embodiment in which the controller 4 stops the GC/compactionwhen a WAF (write amplification factor) is may be degraded due to theGC/compaction, will be described.

FIG. 30 is a flowchart showing an example of the write operation of thehost 2 in the storage system 1 according to the ninth embodiment. FIG.31 is a flowchart showing an example of the write operation of the SSD 3in the storage system 1 according to the ninth embodiment.

As shown in FIG. 30 , in S102G, the host 2 sets the target period, theSLC write disable time, the SLC write enable time, the target capacityof the free blocks, and a WAF limit value W.

In S104, the host 2 determines whether a current time is the SLC writedisable time. If the host 2 determines that the current time is not theSLC write disable time (NO in S104), the host 2 repeats thedetermination in S104 until the SLC write disable time.

If the host 2 determines that the current time is the SLC write disabletime (YES in S104), the host 2 sends the target capacity information tothe SSD 3 in 3802. The host 2 may send the target capacity informationas the target capacity designation command. The target capacity of thefree blocks is the capacity described in the fifth embodiment.

After S802, the host. 2 sends the WAF limit value W to the SSD 3 inS804. The host 2 may send the WAF limit value W as a WAF limit valuedesignation command. The WAF is the ratio of the amount of data actuallywritten into the NAND flash memory 5 to the amount of write data sentfrom the host 2, and becomes greater than one by the GC/compaction. Whenthe WAF increases, a program/erase cycle also increases and thus thedegree of wear-out the NAND flash memory 5 increases. In the ninthembodiment, the controller 4 stops the GC/compaction based on the WAF,and the WAF limit value W relates to a stop condition.

After S804, the host 2 sends the SLC write disable command to the SSD 3in S106.

After S106, the host 2 determines in S108 whether a current time is theSLC write enable time. If the host 2 determines that the current time isnot the SLC write enable time (NO in S108), the host 2 repeats thedetermination in S108 until the SLC write enable time.

If the host 2 determines that the current time is the SLC write enabletime (YES in S108), the host 2 sends the SLC write enable command to theSSD 3 in S110 and ends the operation. If there is data to be written,the host 2 sends the write command to the SSD 3 in S112.

Note that the order of sending the target capacity information and theWAF limit value W may be reversed. Instead of sending the targetcapacity information, the WAF limit value W, and the SLC write disablecommand separately, they can be sent simultaneously. For example, thetarget capacity information and the WAF limit value W may be included inthe parameters of the SLC write disable command.

The operation in FIG. 30 is based on the operation of the host 2 in thefirst embodiment shown in FIG. 5 , but may be based on the operation ofthe host 2 in the modification to the first embodiment shown in FIG. 8 .In the latter case, S802 of sending the target capacity information tothe SSD 3 and S804 of sending the WAF limit value W to the SSD 3 areexecuted before S144 of sending the SLC write disable command to the SSD3 shown in FIG. 8 .

In the SSD 3, as shown in FIG. 31 , upon receiving the target capacityinformation from the host 2 in S812, the controller 4 divides the targetcapacity by the size of the block of data to be written in the SLC modeto calculate the target number of the free blocks required to achievethe target capacity of the free blocks in S814.

After S3814, the controller 4 receives the WAF limit value W from thehost 2 in S816.

After S3816, upon receiving the SLC write disable command from the host2 in S122, the controller 4 sets the write mode to the TLC mode in S124.Then, when the controller 4 receives the write data from the host 2, thecontroller 4 writes the data into the TLC write destination block 126 ofthe NAND flash memory 5 as shown in FIG. 3 .

When the host 2 changes a method of sending the target capacityinformation, the WAF limit value W, and the SLC write disable commandfrom the example shown in FIG. 30 , the controller 4 changes a method ofreceiving the target capacity information, the WAF limit value W, andthe SLC write disable command in accordance with the sending method.

After S124, the controller 4 determines in S822 whether the number ofthe free blocks exceeds the target number of the free blocks.

When the controller 4 determines that the number of the free blocksexceeds the target number of the free blocks (YES in S822), thecontroller 4 ends the operation. When the controller 4 receives thewrite data from the host 2, the controller 4 writes the data into theTLC write destination block 126 of the NAND flash memory 5, as shown inFIG. 3 .

When the controller 4 determines that the number of the free blocks doesnot exceed the target number of the free blocks (NO in S822), thecontroller 4 selects a target block for the GC/compaction in S824 andsets the selected block as a copy source block. An example of a methodof selecting the target block is to select the blocks in an increasingorder of the amount of valid data. Another example of the selectingmethod is to select a block or blocks which store cold data that isunlikely to be overwritten in the future and which does not exceed theWAF limit value.

After 3824, the controller 4 acquires a size of valid data D in thetarget block for the GC/compaction in S826 and determines whether(D+B)/B is equal to or smaller than W in S828. B is the data size of theblock. (D+B)/B represents a WAF in which data of size D is written bythe current GC/compaction and data of size B will be written in thefuture. In S828, therefore, the controller 4 determines whether the WAFis degraded by the WAF limit value W or more.

If the controller 4 determines that (D+B)/B≤W is satisfied (YES inS828), the controller 4 executes the GC/compaction in S830. After S830,the controlled 4 executes the determination in S822.

If the controller 4 determines that (D+B)/B≤W is not satisfied (NO inS828), the controller 4 ends the operation.

FIG. 32 is a graph showing an example of changes in the WAF in theGC/compaction. Assume that the target number of the free blocks is threeand clocks BLK1, BLK2, and BLK3 can be selected as the copy sourceblock. The size of the valid data of the blocks BLK1, BLK2, and BLK3 are25%, 50%, and 75%, respectively. The WAF limit value W is set to 1.5.

First, the block BLK1 is selected as the copy source block. The WAF is1.25, the determination in S826 is YES, and the GC/compaction isexecuted in S303.

Then, the block BLK2 is selected as the copy source block. The WAF is1.5, the determination in S828 is YES, and the GC/compaction is executedin S803.

Finally, the block BLK3 is selected as the copy source block. The WAF is1.75, the determination in $828 is NO, and the GC/compaction is notexecuted.

According to the ninth embodiment, when the WAF is likely to be degradeddue to the GC/compaction, the GC/compaction is stopped, with the resultthat the degree of wear-out of the NAND flash memory 5 does notincrease.

TENTH EMBODIMENT

In the ninth embodiment, the performance of the GC/compaction iscontrolled based on the WAF related to one GC/compaction. Next is adescription of a tenth embodiment in which the GC/compaction iscontrolled based on the average value of the WAF after the start of theGC/compaction.

FIG. 33 is a flowchart showing an example of the write operation of thehost 2 in the storage system 1 according to the tenth embodiment. FIG.34 is a flowchart showing an example of the write operation of the SSD 3in the storage system 1 according to the tenth embodiment. FIG. 35 is agraph showing an example of changes in the WAF in the write operation ofthe SSD 3 according to the tenth embodiment.

As shown in FIG. 33 , the operation of the host 2 in the tenthembodiment differs from the operation in the ninth embodiment in thefollowing two points. 3102G (FIG. 30 ) of setting the target period, theSLC write disable time, the SLC write enable time, the target capacity,and the WAF limit value W is changed to S102H (FIG. 33 ) of setting thetarget period, the SLC write disable time, the SLC write enable time,the target capacity, and a WAF average limit value W2. S804 (FIG. 30 )of sending the WAF limit value W to the SSD 3 is changed to S806 (FIG.33 ) of sending the WAF limit average value W2 to the SSD 3.

As shown in FIG. 34 , the operation of the SSD 3 in the tenth embodimentdiffers from the operation in the ninth embodiment in the followingthree points. S816 (FIG. 31 ) of receiving the WAF limit value W fromthe host 2 is changed to S904 (FIG. 34 ) of receiving the WAF limitaverage value W2 from the host 2. S914 (FIG. 34 ) of calculating theaverage value of the WAF is added after S826 (FIG. 31 ) of acquiring thesize of the valid data D from the target block for the GC/compaction.S828 (FIG. 31 ) of determining whether (D+B)/B is equal to or smallerthan W is changed to S916 (FIG. 34 ) of determining whether the averagevalue of the WAF is equal to or smaller than the WAF limit average valueW2.

FIG. 35 is a graph showing an example of changes in the WAF in theGC/compaction. Assume that the target number of the free blocks is threeand blocks BLK1, BLK2, and BLK3 can be selected as the copy sourceblock. The size of the valid data of the blocks BLK1, BLK2, and BLK3 are25%, 50+, and 75%, respectively. The WAF limit value W2 is set to 1.5.

First, the block BLK1 is selected as the copy source block. The WAF is1.25, the determination in S916 is YES, and the GC/compaction isexecuted in S830.

Then, the block BLK2 is selected as the copy source block. The WAFaverage value is 1.375, the determination in $916 is YES, and theGC/compaction is executed in S830.

Finally, the block BLK3 is selected as the copy source block. The WAFaverage value is 1.5, the determination in S916 is YES, and theGC/compaction is executed in S830.

According to the tenth embodiment, too, when the WAF is likely to bedegraded due to the GC/compaction, the GC/compaction is stopped, withthe result that the degree of wear-out of the NAND flash memory 5 doesnot increase.

While certain embodiments have been described, these embodiments havebeen presented by way of example only, and are not intended to limit thescope of the inventions. Indeed, the novel embodiments described hereinmay be embodied in a variety of other forms; furthermore, variousomissions, substitutions and changes in the form of the embodimentsdescribed herein may be made without departing from the spirit of theinventions. The accompanying claims and their equivalents are intendedto cover such forms or modifications as would fall within the scope andspirit of the inventions.

What is claimed is:
 1. A storage device connectable to a host,comprising: a nonvolatile memory; and a controller configured to controlthe nonvolatile memory, wherein the controller is configured to select afirst mode as a write mode to write data from the host to thenonvolatile memory when receiving a first instruction from the host;n-bit data is written into a memory cell in a first area of thenonvolatile memory in the first mode; n is a positive integer more thanor equal to 1; the controller is configured to select a second mode asthe write mode when receiving a second instruction from the host, m-bitdata is written into a memory cell of a second area of the nonvolatilememory in the second mode, m is a positive integer more than n, and thecontroller is configured to stop executing a write operation in thefirst mode when a write data size in the first mode reaches a targetsize of data written in the first mode, the target size of data writtenin the first mode being specified by a third instruction from the host.2. The storage device of claim 1, wherein the controller is configuredto stop executing a write operation in the first mode when a data writeperiod in the first mode reaches a target period of a data write periodin the first mode, the target period of a data write period in the firstmode being specified by a fourth instruction from the host.
 3. Thestorage device of claim 1, wherein the controller is configured toselect the second mode as the write mode after the controller stopsexecuting a write operation in the first mode.
 4. The storage device ofclaim 1, wherein the nonvolatile memory includes blocks, each of theblocks being a unit of data erase; each of the blocks is an active blockstoring valid data and a free block storing no valid data; and thecontroller is configured to execute a free block generation operation toincrease a number of the free blocks in the first area when receivingthe second instruction.
 5. The storage device of claim 4, wherein thefree block generation operation includes a garbage collection or acompaction.
 6. The storage device of claim 4, wherein the controller isconfigured to stop executing the free block generation operation when asize of the free blocks included in the first area reaches a target sizeof free blocks included in the first area, the target size of freeblocks included in the first area being specified by a fifth instructionreceived from the host after starting the free block generationoperation.
 7. The storage device of claim 4, wherein the controller isconfigured to stop executing the free block generation operation when anexecution time of the free block generation operation reaches a targetexecution time of the free block generation operation, the targetexecution time of the free block generation operation being specified bya sixth instruction from the host.
 8. The storage device of claim 4,wherein the controller is configured to adjust a priority of the freeblock generation operation such that a degradation degree of writeperformance does not exceed an acceptable value of a degradation degreeof write performance due to the free block generation operation, theacceptable value of a degradation degree of write performance due to thefree block generation operation being specified by a seventh instructionfrom the host.
 9. The storage device of claim 8, wherein the writeperformance includes at least one of a throughput and a latency.
 10. Thestorage device of claim 4, wherein the controller is configured toadjust a priority of the free block generation operation such that asize of the free blocks in the first area reaches a target size of freeblocks in the first area, the target size of free blocks in the firstarea being specified by an eighth instruction received from the hostafter starting the free block generation operation.
 11. The storagedevice of claim 4, wherein the controller does not execute a copyoperation for copying valid data in an active block to another activeblock when-a degree of wear of the nonvolatile memory will exceed atarget value of a degree of wear of the nonvolatile memory beforeexecuting the copy operation, the target value of a degree of wear ofthe nonvolatile memory being specified by a ninth instruction from thehost.
 12. The storage device of claim 4, wherein the controller does notexecute a copy operation for copying valid data in an active block toanother active block when-an average of degrees of wear of thenonvolatile memory will exceed a target value of a degree of wear of thenonvolatile memory before executing the copy operation, the target valueof a degree of wear of the nonvolatile memory being specified by a ninthinstruction from the host.
 13. A storage system comprising: a host; anda storage device connectable to the host, wherein the host is configuredto transmit a first instruction and a second instruction to the storagedevice; the storage device includes a nonvolatile memory and acontroller configured to control the nonvolatile memory; the controlleris configured to select a first mode as a write mode to write data fromthe host to the nonvolatile memory when receiving the first instructionfrom the host; n-bit data is written into a memory cell in a first areaof the nonvolatile memory in the first mode; n is a positive integermore than or equal to 1; the controller is configured to select a secondmode as the write mode when receiving the second instruction from thehost; n-bit data is written into a memory cell of a second area of thenonvolatile memory in the second mode, m is a positive integer more thann, and the controller is configured to stop executing a write operationin the first mode when a write data size in the first mode reaches atarget size of data written in the first mode, the target size of datawritten in the first mode being specified by a third instruction fromthe host.
 14. A control method for controlling a nonvolatile memory,comprising: selecting a first mode as a write mode to write data from ahost to the nonvolatile memory when receiving a first instruction fromthe host, selecting a second mode as the write mode when receiving asecond instruction from the host, stopping executing a write operationin the first mode when a write data size in the first mode reaches atarget size of data written in the first mode, the target size of datawritten in the first mode being specified by a third instruction fromthe host, wherein n-bit data is written into a memory cell in a firstarea of the nonvolatile memory in the first mode, n is a positiveinteger more than or equal to 1, m-bit data is written into a memorycell of a second area of the nonvolatile memory in the second mode, andm is a positive integer more than n.
 15. The storage system of claim 13,wherein the host is configured to determine a first mode disable time, afirst mode enable time, and the target size of data written in the firstmode, transmit the second instruction to the storage device when acurrent time is the first mode disable time, and transmit the thirdinstruction and the first instruction to the storage device when acurrent time is the first mode enable time.
 16. The storage system ofclaim 15, wherein the host is configured to transmit the firstinstruction to the storage device after transmitting the thirdinstruction.